In advanced semiconductor fabrication technologies, the photoresist resolution performance is constrained from improving beyond the 22-nm node due to the lithographic limitations of available fabrication technologies and equipment. However, efforts have been made to extend the life cycle of purchased fabrication equipment in order to facilitate development processes and reduce expenditure. Multi-patterning lithography methods are commonly discussed among the alternative solutions.
Multi-patterning lithography (MPL) involves exposing lithographic patterns on a single layer of a substrate using two or more different masks. Different masks are used sequentially to pattern the same layer. The circuit features on each mask are designed to comply with the requirement for relevant minimum separation distance. As a result, the combined circuit layout formed using the multiple masks may generate a smaller feature spacing than the minimum separation distance predetermined for the single-patterning approach. The effective feature pitch can be shrunk further in a cost-efficient way without deteriorating chip performance.